Organizers:
Bernabé Linares-Barranco and Angel Rodríguez-Vázquez
Dept. of Analog and Mixed-Signal Circuit Design, Microelectronics National Center (Sevilla). Ed. CICA, Av. Reina Mercedes s/n, 41012 Sevilla, SPAIN. FAX: 34-5-4231832; Phone: 34-5-4239923; email: bernabe@cnm.us.es
DESCRIPTION OF THE WORKSHOP:
Developing hardware for neural applications is a task that hardware engineers have faced during the past years using two distinct main approaches:
(a) producing "general purpose" usually-digital neuro-computing systems or "neural-accelerators" with a certain degree of flexibility to emulate different neural architectures and learning rules.
(b) developing "special purpose" neuro-chips, mostly using analog or mixed analog/digital circuit techniques, intended to solve a specific problem with very high speed and efficiency.
Usually hardware of task (b) is used for the front end of a neural processing system, such as sensory data (image/sound) adquisition and sometimes with some extra (pre)processing functionality (noise removal, automatic gain, dimensionality reduction). On the other hand, hardware of task (a) is employed for more "intelligent" or higher level processing such as learning, clustering, recognition, abstraction, and conceptualization. However, the limits of hardware of type (a) and (b) are not very clear, and as more hardware is developed the overlap between the two approaches increases.
Digital technology provides larger accuracy in the realization of mathematical operations and offers great flexibility to change learning paradigms, learning rules, or to tune critical parameters. Analog technology, on the other hand, provides very high area and power efficiency, but is less accurate and flexible. It is clear that people that are developing neural algorithms need to have some type of digital neurocomputer system where they can change rapidly the neural architecture, the topology, the learning rules, try different mathematical functions, and all that with sufficient flexibility and computing power. On the other hand, when neural systems require image or sound adquisition capabilities (retinas or cochleas) analog technology offers very high power and chip area efficiency, so that this approach seems to be the preferred one. However, what happens when it comes to develop a hardware system that needs to handle the sensory data, perform some basic processing, and continue processing up to higher level stages where data segmentation has to be performed, recognition on the segments has to be achieved, and learning and abstraction should be fulfilled? Is there any clear border among analog and digital techniques as we proceed upwards in the processing cycle from signal acquisition to conceptualization? Is it possible to take advantage of the synergy between analog and digital? How? Are these conclusions the same for vision, hearing, olfactory, or intelligent control applications?
The purpose of this workshop is first to join state-of-the-art neural engineers representative of both hardware approaches, establish the advantages and limitations of the two, and discuss how to link or fuse them in order to develope neural hardware systems that efficiently cope with all the processing stages, from the sensory up to the abstraction tasks.
The topic is of great controversy since the overlap between the two hardware approaches is increasing every day. As the need for more complete neural systems grows, engineers of type (b) have to incorporate more "intelligent" processing, and engineers of type (a) need to go closer to the raw sensory data.
We believe it is a good point in time to make a debate between representatives of the two approaches, since both have evolved independently into a large enough degree of development and maturity as to enable pros and counters be discussed on the basis of objective, rather than subjective considerations.
LENGTH AND FORMAT OF THE WORKSHOP:
The length of the workshop would be of one day with two sessions. In the first session the speakers would be representative of hardware approach (a), and in the second session of hardware approach (b).
SPEAKERS (For brief abstracts and biographies click HERE)
1. Xavier Arreguit, CSEM, Neuchatel, Switzerland
"Analog VLSI for Perceptive Systems"
2. Andreas Andreou, John Hopkins University, Baltimore, Maryland, U.S.A.
"Silicon Retinas for Contrast Sensitivity and Polarization Sensing"
3. Taher Daud, Jet Propulsion Laboratory, Pasadena, California, U.S.A.
"Focal Plane Imaging Array-Integrated 3-D Neuroprocessor"
4. Yuzo Hirai, Institute of Information Sciences and Electronics, University of Tsukuba, Japan.
"PDM Digital Neural Networks"
5. Marwan Jabri, University of Sydney, Australia.
"On-Chip Learning in Analog VLSI and its Application in Biomedical Implant Devices"
6. Nelson Morgan, University of California, Berkeley, U.S.A.
"Using A Fixed-point Vector Microprocessor for Connectionist Speech Recognition Training"
7. Ulrich Ramacher, University of Technology, Dresden, Germany.
Title to be announced
8. Tadashi Shibata, Tohoku University, Sendai, Japan.
"Neuron-MOS Binary-Analog Merged Hardware Computation for Intelligent Information Processing"