1. Eric Vittoz (or Xavier Arreguit), CSEM, Neuchatel, Switzerland

Abstract to be posted.

Biography to be posted.

2. Andreas Andreou, John Hopkins University, Baltimore, Maryland, U.S.A.

"Silicon Retinas for Contrast Sensitivity and Polarization Sensing". ABSTRACT: Maximizing the information capacity of the sensory channels at the transduction level under the physical constraints imposed by the actual hardware is a reasonable objective for any system that has to extract information from the environment in an energetically efficient way. Key to the success in such endeavor is the utilization of prior information. We describe two hardware systems that achieve the above goal in two different ways. The first, is a contrast sensitive silicon retina which through adaptation (local gain control) is capable of handling wide dynamic range stimuli within a single image. The second system is a silicon retina for polarization sensing. Intensity based imagers provide only spatial and temporal scalar information about the imaged scene. A polarization sensor provides a three component vector for each pixel in the array.

3. Taher Daud, Center for Space Microelectronics Technology, Jet Propulsion Laboratory, Pasadena, California, U.S.A.

"Focal Plane Imaging Array-Integrated 3-D Neuroprocessor". ABSTRACT: A particularly challenging problem in image processing is encountered by a fast frame seeker on an interceptor in its mission, lasting only a few seconds, for spatio-temporal recognition of point and resolved targets, to accomplish its time-critical functions of target acquisition, discrimination, and homing. JPL/Irvine Sensors Corporation collaborative team is currently developing an analog 3-dimensional, low-power neuroprocessor (a size of a sugarcube), directly interfaced with a focal plane imaging array for a fully parallel image transfer, to address this on-board application. In this presentation, the 3-D neuroprocessing architecture and its hardware implementation based on the z-plane (stacking) technology will be discussed. The focus will be on the development of an all parallel image acquisition and processing architectures to achieve unprecedented speed in image processing. By mating an imaging (infrared sensor) array to a 3-D packaged stack of neural-net ICs along respective edges, every pixel of the sensor array would directly input an analog signal into a neural network, thereby processing the whole image with full parallelism. The first generation product would be configured to perform eight-bit multiplies per second with 64x64 templates, and would provide image processing with the speed of ~1000 frames/sec. This involves (i) over 13000 indium bump contacts, (ii) over 250,000 fully programmable, low-power 8-bit MDAC-based synaptic weights, and (iii) a high weight change speed of 2 gigabits per second. Overall, the sugarcube is designed to consume only ~2.5 watts of power. A reconfigurable neural architecture would discriminate targets from clutter or classify targets once resolved. Furthermore, a variety of neural algorithms such as backpropagation, cascade error projection, and template matching could be incorporated on each chip with software programmability.

Taher Daud, Tuan Duong, Anil Thakoor, Center for Space Microelectronics Technology Jet Propulsion Laboratory, California Institute of Technology Pasadena, California and David Ludwig, Chris Saunders, John Carson, Irvine Sensors Corporation, Costa Mesa, California. Sponsored by BMDO, ONR, ARPA, and NASA

BIOGRAPHY: Taher Daud received his BS degree in electrical engineering from the University of Jabalpur, India, and MS and Ph.D. in solid-state electronics in 1976 and 1979 respectively from the University of California, Los Angeles. He joined the Jet Propulsion Laboratory in 1976 and worked on the development of high efficiency silicon solar cells and ribbon silicon technologies for the Flat-Plate Solar Array Project until 1985. He has also been involved in the development of laser-operated solar cells, molecular beam evaporation technique for solar cells, and silicon-compatible modulation doped silicon structures for infrared sensors. During 1985-87, he worked on the development of backside illuminated CCDs for NASA's Wide Field/Planetary Camera program to develop a theoretical understanding of back-side-illuminated ultraviolet and short wave sensitive sensors. Since 1987 he has worked in the area of electronic implementation of neural networks and analog parallel processing devices, and is involved with thin film and VLSI device and architecture development. He has published/presented over 60 papers, and has authored several patents.

4. Yuzo Hirai, Institute of Information Sciences and Electronics, University of Tsukuba, Japan.

"PDM Digital Neural Networks". ABSTRACT: In this talk I will describe a PDM (Pulse Density Modulating) digital neural network system which we have developed. An advantage of using PDM is that it allows to transmit analog outputs by single lines as our real neurons do. Another advantage of using digital circuits is that it allows high precision and high scalability. These two advantages are necessary to develop a large scale neural network. Another important point of our real neural networks is the omnipresence of feedback connections. Even in retinal circuits, feedback exists at every processing stage. In order to express feedback, we need to solve at least the first order differential equations. The hardware we have develop has these advantages and functions. After introducing our hardware, I will briefly describe our future plan to implement sensory processings in our network.

BIOGRAPHY: Yuzo Hirai received the B.S., M.S., and Ph.D. degrees in electrical engineering from Keio University, Yokohama, Japan, in 1970, 1972 and 1975, respectively. He was with Fujitsu Co., Kawasaki, Japan, from 1975 to 1978. From 1978 to 1981, he was a research assistant of the Institute of Information Sciences and Electronics, University of Tsukuba, Ibaraki, Japan. From 1981 to 1985, he was a assistant professor, from 1985 to 1992, he was a associative professor, and since 1992, he has been a professor of the same institute. His research interest are in neural networks including stereo vision, pattern recognition, associative memory and hardware implementation of neural networks. He is a member of the IEEE, the INNS and the IEICE of Japan.

5. Marwan Jabri, University of Sydney, Australia.

"On-Chip Learning in Analog VLSI and its Application in Biomedical Implant Devices"

BIOGRAPHY: Received a License de Physique and a Maitrise de Physique from Universite de Paris VII, France, in 1981 and 1983 respectively, and a PhD in Electrical Engineering in 1988 from Sydney University. Positions held: Lecturer in Electrical Engineering, 1988-1991, Senior Lecturer 1992-1994, Reader in Electrical Engineering 1994-.Recipient of the 1992 Australian Telecommunication and Electronics Research Board (ATERB) Outstanding Young Investigator medal. Author, co-author and editor of 3 books and over 100 technical papers and four patents. Senior member of the Institute of Electrical and Electronic Engineers, U.S.A. Member of the editorial board of serveral journals in the area of VLSI systems and neural computing.

6. Nelson Morgan, University of California, Berkeley, U.S.A.

"Using A Fixed-point Vector Microprocessor for Connectionist Speech Recognition Training". (Nelson Morgan and David Johnson). ABSTRACT: Over the last few years at ICSI/UC Berkeley members of our working group have developed a chip that combines a general purpose RISC microprocessor core with 16 closely coupled fixed point arithmetic pipelines. The main processor provides a general programming capability, while the parallel arithmetic units are targeted at a class of target algorithms, gaining a perfomance advantage from using moderate precision ALUs and a simple data parallel architecture.Using the industry standard MIPS-II instruction set for main CPU allows the use of existing tools, and incorporating the fixed point ALUs in the form of a vector extension to the instruction set enhances programmability for a nominal additional cost in silicon.

We have recently fabricated some prototype S-bus boards with this chip and some fast SRAM. We have used the boards for experiments with training large Multi-layer Perceptrons that we use for phonetic probability estimation in speech recognition. The theoretical peak performance of the chip, running at 40 MHz, is about 1 billion operations per second (including memory ops). Depending on the network size, we are currently getting between 30 and 70 Million connection updates per second using 16 bit multipliers and 32 bit accumulations. We expect these figures to rise somewhat as we further optimize our I/O (the figures include the cost of the complete problem, including getting patterns from disk) and begin to block some of the learning. We are currently in the process of doing a production run, and have plans to build machines using multiple chips.

We expect to quickly review a few features of this chip (which is the topic of an oral presentation at the Denver meeting), but then discuss aspects of using such a chip for a full application, which for our case is statistical training for speech recognition.

7. Ulrich Ramacher, University of Technology, Dresden, Germany.

Abstract to be posted.

Biography to be posted.

8. Tadashi Shibata, Tohoku University, Sendai, Japan.

Abstract to be posted.

Biography to be posted.